发明名称
摘要 PURPOSE:To speed up processing and to simplify hardware constitution, by decoding MH and MR codes principally through software in parallel. CONSTITUTION:Code data RD is written successively in a restoration buffer memory 10 with a capacity of 2-4K by dividing by 16-bit data from the head. They are read out in parallel during MH restoration and compared with MH codes to obtain run length RL, which is written in memories 20 and 22. Data converted into RL one line before and stored in the memory 20 is used as reference line data during MR demodulation and the data is read out of the memory 10 to obtain MR codes; and the RL is obtained by arithmetic processing based upon the reference line data and written in the memory 20. Then, a recording picture signal RPS is outputted to an RL counter 32 and a recording circuit 30.
申请公布号 JPS6341270(B2) 申请公布日期 1988.08.16
申请号 JP19820107967 申请日期 1982.06.23
申请人 FUJITSU LTD 发明人 OGAWA SATOSHI;IIZUKA YOSHIO;MATSUNAGA SHIGEO
分类号 H04N1/417;H04N1/419 主分类号 H04N1/417
代理机构 代理人
主权项
地址