| 摘要 |
PURPOSE:To increase the arithmetic processing speed for addition/subtraction of floating points in consideration of a rounding mode, by using a detecting circuit for cancelling bit train. CONSTITUTION:The right arithmetic shift data of the positive significance is set at O (where O0 is defined as a most significant bit MSB) with On-1 defined as a least significant bit LSB respectively. Then a signal level opposite to the signal level set on a route 13 is outputted to an output terminal 15 in response to the change of the signal level of the route 13. At the same time, a bit train taken down from (n) digits at the time of the right arithmetic shift, i.e., a cancelling bit train is outputted to a route 25 as a signal level of the negative significance with -Zo and -Zn-1 set opposite to the MSB and the LSB respectively. A zero detecting circuit 16 decides whether (n) pieces of signals levels on the route 25 are all set at H levels or not. The result of this decision is outputted to an output terminal 17 in the form of the 1-bit information show ing the presence of absence of a bit taken down at the time of the right arithme tic shift. |
