发明名称 Test interface for an MOS technology integrated circuit
摘要 This interface enables the integrated circuit with which it is associated to be placed in a test configuration by applying to its test input terminal (2) a voltage higher than the power supply voltage (Vcc) of the circuitry. In the rest state, the interface then supplies a low logic level to its output terminal (5). If the test command voltage is applied, this level changes state. The interface comprises, in particular, two transistors (M1, M2) of opposite types of conductivity which are fed by a constant current source (10, M5, M6). The interface switches over when the input transistor (M1) is put into the conducting state by the test command voltage so as to divert a fraction of the current flowing in the second transistor (M2). The input terminal (2) can at the same time be a functional input terminal of the integrated circuit.
申请公布号 US4764924(A) 申请公布日期 1988.08.16
申请号 US19860918168 申请日期 1986.10.10
申请人 BENDIX ELECTRONICS S.A. 发明人 MATE, JEAN-LUC
分类号 H01L21/822;G01R31/28;G01R31/317;G01R31/3185;H01L27/04;(IPC1-7):G01R31/28 主分类号 H01L21/822
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