| 摘要 |
PURPOSE:To ensure the input of the correct data to a subsequent arithmetic element as the valid data even though data are intermittently outputted from a arithmetic element, by delaying a writing or reading action against the same bank when the bank to be written next is equal to the bank to be read out next. CONSTITUTION:The written data is read out of one of two memory means 47 and 48 and can be sent to another arithmetic means while the output data on an arithmetic means is written into both means 47 and 48 owing to the control of a control means 100 even in case the output of said arithmetic means is delivered intermittently. Thus a reading or writing action is possible to the means 47 and 48 with no large delay since both means 47 and 48 consist of plural data banks. |
