| 摘要 |
PURPOSE:To eliminate the restriction for transfer data length by enabling successively a decoder decoding a bus select data by a bus control signal, and storing successively an image data in an image memory. CONSTITUTION:When a horizontal direction picture element number (m) of image memories 14, 15, and a one horizontal direction picture element number (n) of an image data are in a relation of (m)<(n), a CPU 11 gives 3 and 2 to decoders 21, 22 as a bus select data BS1, and BS2, respectively. To a decoder selecting circuit 23, a bus control signal BS of an L level is applied, and the decoder 21 becomes enable. The decoder 21 decodes 3 and varies an output to an L level, and the image data is inputted to the memory 14. When the number of transfer data reaches (m), the CPU 11 makes the signal BC an H level, the decoder 22 is selected and the memory 15 is selected, and the image data extending from the (m)+1-th one to the (n)-th one are stored in the memory 15, therefore, an image processing of a wide application range can be executed.
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