发明名称 HIGH SPEED RECEPTION PROCESSING SYSTEM
摘要 PURPOSE:To prevent reception overrun by setting an address and a byte count value in response to a long buffer to a register group on an I/O when a received long buffer is ensured after a reception buffer busy takes place and the next frame is received. CONSTITUTION:If a reception buffer busy takes place, the release of the reception buffer busy is detected and a long buffer is given, then a head address of a long buffer is stored in a work area of a tentative RAM 3, then an RNR frame of a P-bit is sent to await the frame reception. Moreover, in receiving a response frame of F-bit, normal high speed reception processing is applied by the hardware. Thus, the reception overrun caused by receiving an I-frame in a extrabuffer does not take place and the reception is attained without error.
申请公布号 JPS63196135(A) 申请公布日期 1988.08.15
申请号 JP19870029039 申请日期 1987.02.10
申请人 CANON INC 发明人 MAEKAWA YOSHITO
分类号 H04L29/08;H04L13/00;H04L13/18 主分类号 H04L29/08
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