| 摘要 |
PURPOSE:To easily generate a pattern which confirms the normalcy of an ECC circuit, by providing a data inverting circuit, which inverts write data to a memory by memory address information, for each write data bit. CONSTITUTION:Inverting circuits 500, 501, 516, and 531 are data inverting circuits corresponding to bits 00, 01, 16, and 31 respectively. The circuit 500 inverts data D0 only when an address A0 and address A18 are logical '1' and logical '0' respectively and a maintenance designating circuit 13 is effective. That is, data is inverted from '0' to '1' or from '1' to '0'. Data inverting circuits 501-531 corresponding to data bits D1-D31 are operated similarly. Meanwhile, data D0-D31 are inputted to an ECC circuit 12 as they are, and a check code corresponding to these data is outputted to bits C0-C7. Thus, an optional data bit can be inverted.
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