| 摘要 |
PURPOSE:To make the provision of a counter unnecessary, by providing an FF which inverts and holds the least significant bit of a parallel data, detecting the completion of a conversion operation by the propagation of the above n-bit values from a first bit to the (n-1)-th bit of a shift register of n-bits, and generating the next parallel load signal. CONSTITUTION:When the parallel data is set at the shift register 1 of n-bits, the inverted data of the least significant bit of the above data is set at the FF4. Afterwards, the data inputted to the register 1 is shifted out in order, and simultaneously, the bit value held by the FF4 is inputted to a final stage. At a time when an n-th bit is shifted to the most significant bit, the data from the (n-1)-th bit to the least significant bit becomes the same data as that of the FF4. A coincidence circuit 3 detects the above state, and recognizes it as the completion of conversion, and generates the parallel load signal on the register 1 with the next clock. Hereafter, the above operation is repeated at every n-bits. |
