SEMICONDUCTOR INTEGRATED CIRCUITS CONTAINING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICES

摘要

A CMOS integrated circuit device which avoids latchup between closely spaced apart n-channel and p-channel FETs (90, 130) of the device includes a latchup-preventing trench (150) formed in the semiconductor substrate (20) between the FETs. The trench is essentially completely filled with a solid dielectric material (160) essentially free of crack-inducing voids, and achieves a narrow width because the angle between the trench sidewall and a perpendicular drawn to the substrate surface (50) is greater than, or equal to, about 5 degrees but less than about 10 degrees.