| 摘要 |
PURPOSE:To obtain a speed increasing mechanism for high-performance by using two propagation arithmetic systems incorporated in respective processors and advancing two kinds of propagation arithmetic by the processors in parallel. CONSTITUTION:Oscillation processors are assigned by loading '1' in the control register 19 of a processor 1 in the processor block 20 at the leftmost end and '0' in other registers 19. While an address A0 of a storage part is accessed by each processor, an ALU 11 is set to addition and when propagation addition is started, an upper ad a lower propagation arithmetic system constituted in each block by cascading ALUs 11a and 11b perform 1-bit propagation addition regarding the address A0 in parallel as to both cases wherein an input is '0' or '1', so that the sum of the output is determined by the block 20 at the left end when the addition is finished. The determined sum is stored in the address A0 and its carry is stored in a register 18. similar processing is repeated as to A1-An of the storage part. |
