| 摘要 |
PURPOSE:To speed up the effective transfer rate of data by fetching plural continuous data by a block buffer register and transferring them all at once to a buffer memory via parallel processing. CONSTITUTION:Data received from an input/output processor IOP1 via a data bus 4 by a transfer request given from the IOP1 are fetched by a block buffer register 30. When this register 30 is filled with plural data, the transfer requests given from the IOP1 are discontinued temporarily. At the same time, a using request RQa given to a buffer memory 32 is sent to a control circuit. Then the circuit 33 sends back the using permission AKa of the memory 32 as long as this memory is ready. As a result, the plural continuous data stored in the register 30 are transferred all at once to the memory 32 via the parallel processing and stored there. Thus the interrupted transfer is started again at the side of the IOP1. Then the effective data transfer speed is increased.
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