| 摘要 |
PURPOSE:To avoid the increase of the hardware quantity by using a group of address registers for access control of a medium-speed memory to restore an address state required for re-execution when an error occurs. CONSTITUTION:If a 1-bit error is produced from the data (microinstruction codes) read out of a high-speed memory HCS 1 or a medium-speed memory LCS 3, an error correction code control circuit ECCC 12 detects the error for its recovery. For instance, an access is given to the data from the LCS 3 and then also from the LCS 3. In such a case, a 1-bit error if detected out of the data read out of the LCS 3 is recovered and at the same time an address is returned via the paths shown by the dotted lines through a medium-speed memory following address register 5, a medium-speed memory address register 4, an actual row address register 6 and the register 5. Thus the error processing procedure is executed again and therefore the increase of the hardware quantity is avoided.
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