发明名称 ADDRESS GENERATING CIRCUIT
摘要 PURPOSE:To realize the effective utilization of a memory by shifting the value of a base address register by a degree equal to the optional number of bits designated by a program and using this shifted value as an actual base address. CONSTITUTION:A shift circuit 14 is provided between the output of a base address register 12 and the input of an adder 13. The circuit 14 shifts the output of the register 12 by a degree equal to the number of bits designated by a program in terms of one of weighting systems. The output of the circuit 14 has the width equal to the number of bits obtained by adding the number of shiftable bits to the high-order bit side of said number of bits after input of the output bit number of the register 12. An adder 13 adds the output of the circuit 14 and the output of an offset address register 11 together to obtain an actual memory address. As a result, the degree of freedom is increased for design of a program.
申请公布号 JPS63192144(A) 申请公布日期 1988.08.09
申请号 JP19870025844 申请日期 1987.02.05
申请人 NEC CORP 发明人 MOTOBAYASHI TOSHIHIKO
分类号 G06F12/02 主分类号 G06F12/02
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