| 摘要 |
PURPOSE:To decrease a peak current at the time of sense by dividing a memory cell array provided on intersections of plural word lines and bit lines, respectively, into plural blocks, bringing a sense amplifier of a selected block at every active cycle to a sense end eariliest, and delaying others. CONSTITUTION:RB1-RB6, SA1a, SA1b-SA4a, SA4b, MB1a, MB1b-MB4a, MB4b, CD1-CD4, and RD denote row blocks, sense amplifiers, memory cell array blocks, column decoders, and a row decoder, respectively. In this constitution, for instance, in case of RA1=1, in the block RB4 (the sense amplifiers SA4a, SA4b) of RA8=1, RA9=1, sense amplifier driving signals phiS81a, phiS81b for driving a transistor are both ended quickly as 'H'. On the other hand, at the time of RA8=1 and RA9=0, a signal level to the row block RB2 (the sense amplifiers SA2a, SA2b) is delayed as 'L' and ended. |
