发明名称 SEMICONDUCTOR TESTER
摘要 PURPOSE:To shorten a checking time, by providing a pattern memory control signal selection circuit, an expectation value memory circuit and a comparing circuit and checking a pattern memory circuit in a hardware manner. CONSTITUTION:A signal selection circuit 23 is controlled by CPU and the checking data stored in a ROM circuit 22 is supplied to a pattern memory RAM circuit 9. After writing operation is finished, the pattern memory RAM circuit 9 becomes a read state and a strobe signal is generated from a pattern memory control signal selection circuit 20 in synchronous relation to the pulse signal from a pattern memory address control circuit 5. A comparing circuit 24 compares the data written in the pattern memory RAM circuit 9 with read data and stops the pattern running of the pattern memory address control circuit 5 when the data are judged to be non-coincidence. CPU monitors whether a pattern has run to the pattern final address of the circuit to check the pattern memory circuit.
申请公布号 JPS63191081(A) 申请公布日期 1988.08.08
申请号 JP19870022979 申请日期 1987.02.03
申请人 OKI ELECTRIC IND CO LTD 发明人 OGATA YASUSHI
分类号 G01R31/28;G01R31/3183;G11C29/10 主分类号 G01R31/28
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