发明名称 BIT INFORMATION COMPRESSION SYSTEM
摘要 PURPOSE:To decrease the delay time produced before the states of all switches are fixed and at the same time to reduce the areas for these switches on an LSI, by controlling a triangular matrix switch with the third output of a triangular matrix. CONSTITUTION:A 1st signal input to be given to an information transmission means Sij decides the propriety for output of A to aj. In other words, a 1st signals to the Sij is equal to '1' together with mi set at '1'. Under such conditions, a 2nd signal output is set at '0' against Si+1,j and hereafter the control is given so that no output is given to aj. At the same time, a 3rd output signal is set at '1' with Cij turned on and di is delivered to aj with control. While a 3rd signal is transmitted to Si+1,j+1 to give an instruction to the Si+1,j+1 and its followers to show that the output is allowed to aj+1. In case the 1st signal to the Sij is equal to '1' with the mi set at '0', the 1st signal input is outputted as it is to the 2nd signal sent from the Sij and '0' is outputted to the 3rd signal. Thus, the mi is taken over by the Si+1,j with no influence. These said actions are carried out by all information transmission means.
申请公布号 JPS63191225(A) 申请公布日期 1988.08.08
申请号 JP19870022321 申请日期 1987.02.04
申请人 HITACHI LTD 发明人 SAKOTA YUKISUKE;NOMI MAKOTO;TSUDA TAKASHI;KAWASAKI SHUNPEI
分类号 G06F7/00;G06T9/00 主分类号 G06F7/00
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