发明名称 PROGRAMMABLE LOGIC ARRAY DEVICE
摘要 PURPOSE:To realize the high density by a method wherein two wiring parts arranged in the gate-width direction can be arranged in individual drain regions in at least one part of drain regions of a group of transistors so that the interval between the wiring parts connected to the drain region can be narrowed. CONSTITUTION:At individual drain electrodes 801-80n, 901-90n for a first and a second MOSFET rows 101, 102 the gate width is widened and two metal wiring parts are arranged on the widened part; a contact hole is connected to only either of the two metal wiring parts. If the individual drain electrodes for the first and the second MOSFET rows 101, 102 are made, in the gate-width direction, to correspond to the two metal wiring parts arranged in the gate- length direction, the number of unused MOSFET's is reduced; the area length of the metal wiring parts is reduced; the high density is realized.
申请公布号 JPS63188954(A) 申请公布日期 1988.08.04
申请号 JP19870020904 申请日期 1987.01.30
申请人 NEC CORP 发明人 KOYABU KUNIHIRO
分类号 H01L21/82;H01L27/112;H03K19/177 主分类号 H01L21/82
代理机构 代理人
主权项
地址
您可能感兴趣的专利