发明名称 PEAK HOLDING CIRCUIT
摘要 PURPOSE:To eliminate the possibility of malfunction due to an offset voltage by controlling an analog switch with the output signal of a logic circuit. CONSTITUTION:A signal input terminal VIN is connected to the uninverted input terminal of a comparing circuit COM and one terminal of an analog switch S. Further, the other terminal of the switch S is connected to the inverted input terminal of the circuit COM and a sampling capacitor CS is connected between their connection point and earth potential and used as an output signal terminal VOUT. Then the output signal of the circuit COM is ANDed by a logic circuit G and inputted to the gate of an MOS transistor (TR) as the switch S. Further, a period where in the circuit COM decides an input potential difference is provided by using a control signal phi and a period wherein the signal phibecomes active when the input signal varies in said period is set. Then the capacitor CS is charged through the switch S to prevent a peak holding circuit from malfunctioning.
申请公布号 JPS63188776(A) 申请公布日期 1988.08.04
申请号 JP19870020909 申请日期 1987.01.30
申请人 NEC CORP 发明人 IGARASHI HATSUHIDE
分类号 H03K5/153;G01R19/04 主分类号 H03K5/153
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