| 摘要 |
PURPOSE:To attain a stable phase period even at the time of high speed retrieving by switching an output voltage of a loop filter of a PLL circuit attended with the switching of a magnetic head. CONSTITUTION:When a head switching signal (SWp) is at a low level, that is, when a head 2 generates an output, a capacitor C2a of the LPF 11 is selected and a signal Swp is at a high level, that is a head 3 generates an output, then a capacitor C2b is selected. The capacitors C2a, C2b hold individually the control voltage (Vd) of a voltage controlled oscillator 12 against the output of the heads 2, 3. When the PLL circuit 13 is once locked and the signal Swp goes to a low potential, the voltage Vd is locked to the output from the head 2 before one revolution of a rotary drum 1 and reaches a holding DC voltage. In such a state, the locking of the circuit 13 is started and locked without frequency error. When the signal Swp goes to a high potential, the locking state is attained immediately from the output start point of the head 3 similarly. |
