| 摘要 |
PURPOSE:To contrive to improve the operating efficiency of a CPU by switching the mode into an asynchronous refresh for a succeeding prescribed period when the execution of the refresh in synchronism with the access of a processor (CPU) is detected consecutively for a prescribed period so as to execute the refresh cycle for a required minimum period. CONSTITUTION:In executing the refresh cycle of a DRAM, when the CAS (column address strobe signal) before RAS (row address strobe signal) refresh inserted just after the CPU applies accessing to the DRAM is executed consecutively for a prescribed period, the refresh is switched into the asynchornizing refresh executed for the refresh period specified by the DRAM. Thus, even if the access frequency of the CPU is increased, the refreshing with a frequency more than the required frequency is not executed and the remarkable reduction in the operating efficiency of the CPU is prevented and the refresh is executed at an optimum period.
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