发明名称 PARITY COUNTING CIRCUIT
摘要 PURPOSE:To apply parity check to even a parallel signal by inputting an exclusive OR result and its inversion to a JK flip flop in a prescribed time zone and double inputting the exclusive OR result to the JK flip flop in the other time zone to subject all data bits constituting the parallel signal to parity counting. CONSTITUTION:In a prescribed determined time zone TSO, an exclusive OR signal (j) outputted from an exclusive OR circuit 100 indicates the logical value of a data bit B1 transmitted by the other data D2. Consequently, the logical value of the data bit B1 is inputted to the J terminal of a JK flip flop 400 as it is and its inversion is inputted to the K terminal of the JK flip flop 400, and counting is started in the JK flip flop 400 from the logical value of the data bit B1. Therefore, parity including bits assigned to a preliminarily determined time zone of the other serial signal is counted. Thus, accurate parity check of even the parallel signal is executed.
申请公布号 JPS63187732(A) 申请公布日期 1988.08.03
申请号 JP19870018993 申请日期 1987.01.29
申请人 FUJITSU LTD 发明人 IKEDA KAZUYOSHI;KAWADA HIROYASU
分类号 H03M13/00 主分类号 H03M13/00
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