发明名称 BURST GATE PULSE FORMING CIRCUIT
摘要 PURPOSE:To properly gate the bursts of respective systems by switching a time constant according to NTSC and PAL systems and switching the pulse duration and the timing of a burst gate pulse. CONSTITUTION:A low voltage at the time of the NTSC and a high voltage at the time of the PAL are impressed to a driving voltage impressing terminal 210 for NTSC/PAL switching. At the time of the NTSC, transistors 205, 206 are turned off and the burst gate pulse 6 at the time of the NTSC has the leading of the pulse decided by the time constant of a resistance 23, an internal capacity 35 from the trailing edge of a horizontal synchronizing signal and the timing of the trailing decided by the time constant of an external resistance 34 and an external capacity 36 externally connected to a synchronizing signal output terminal 7. At the time of the PAL, the transistors 205, 206 are conductive, thereby, transistors 207, 208 are conductive, so that the leading edge time constant of the burst gate pulse 6 at the time of the PAL is decided by the resistance 23, and the internal capacities 35, 209.
申请公布号 JPS63187987(A) 申请公布日期 1988.08.03
申请号 JP19870021554 申请日期 1987.01.30
申请人 MITSUBISHI ELECTRIC CORP 发明人 HASHIMOTO SUGAO
分类号 H04N9/455;H04N9/64 主分类号 H04N9/455
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