发明名称 INTER-FRAME ENCODING DEVICE
摘要 <p>PURPOSE:To execute a control of an inter-frame suppression coefficient without causing a delay by a small scale circuit, by controlling a suppression coefficient of a difference suppressing circuit of an inter-frame encoding processing circuit. CONSTITUTION:A video signal is supplied to an inter-frame encoding processing circuit 6 through an A/D converter 2 and a frame dropping circuit 3, and an encoding output is supplied to a transmission control circuit 10 through a variable length encoding circuit 7 and a buffer memory 8. When the generated information quantity corresponding to one transmission frame in the inter-frame encoding processing circuit 6, and its generation time are denoted by H and S, respectively, an encoding control circuit 9 detects the generated information quantity HX in some time SX, and controls a suppression coefficient of a difference suppressing circuit of the inter-frame encoding processing circuit 6 so that the generated information quantity in some time SX does not exceed a straight line of HX=(H/S)XSX.</p>
申请公布号 JPS63187922(A) 申请公布日期 1988.08.03
申请号 JP19870020000 申请日期 1987.01.30
申请人 NIPPON TELEGR & TELEPH CORP <NTT>;SONY CORP 发明人 SUZUKI HAJIME;HASE MASAHIKO;MORITA HIDEO;KURIHARA AKIRA
分类号 H04N19/50;H03M7/40;H04B14/06;H04N19/105;H04N19/15;H04N19/172;H04N19/196;H04N19/423;H04N19/503;H04N19/587;H04N19/593;H04N19/85;H04N19/91 主分类号 H04N19/50
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