| 摘要 |
PURPOSE:To control wiring length by performing connection within internal blocks and external blocks, and between the internal blocks and the external blocks, by using blocks for wirings consisting of basic cells for the wirings. CONSTITUTION:Basic cells 3 for wirings are arranged among basic cell rows 2 for a master slice type semiconductor integrated circuit and among cell rows 1 for input-output circuits and the basic cell rows 2. A block 10 for the wiring is disposed onto a cell array for the wirings just under an internal block 4 and an internal block 7. An output terminal 5 for the internal block 4 and a connecting terminal 11 for the block 10 for the wiring, an input terminal 8 for the internal block 7 and a connecting terminal 13 for the block for the wiring, an input terminal 9 for the internal block 7 and a connecting terminal 14 for the block 10 for the wiring, and an output terminal 6 for the internal block 4 and a connecting terminal 12 for the block 10 for the wiring are connected respectively. Accordingly, wiring length can be controlled. |
