| 摘要 |
PURPOSE:To secure the characteristic of a digital filter without increasing the number of bits of a register or a computing element by making the sampling frequency of an integral term lower than that of a digital filter. CONSTITUTION:The titled filter is provided with a first register 2 where input data is stored at every sampling period, a second register 12 which accumulates input data stored in the first register at every (2*n+1) sampling period and stores the result, a multiplier 5 which multiplies the output of the second register by a first coefficient, a third register 8 in which the multiplication result of the multiplier is stored, an adder 13 which adds the output of the third register to the output of the first register at every sampling period, and a fourth register 10 which causes the multiplier 5 to multiply the output of the adder by a second coefficient and stores the multiplication result. Thus, the sampling frequency of the integral term of slow response is made lower than that of a proportional term to increase the coefficients of multiplication and the number of bits of registers and the multiplier is reduced.
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