| 摘要 |
PURPOSE:To realize a mini-step drive by varying the duty ratio of pulse signals for phases at a predetermined period. CONSTITUTION:A first clock generator 5 applies a clock signal CLKH of relatively high frequency to a first counter 6, and a counter 6 applies its count CNTH as the lower bits of an address signal to an ROM 7. A second clock generator 8 applies a clock signal CLKL of relatively lower frequency corresponding to the rotating speed of a stepping motor to a second counter 9, and the counter 9 applies its count CNTL as the higher bits of the address signal to the ROM 7. The duty ratios of phase pulse signals D1-D4 from the ROM 7 are varied at a predetermined period, and varied at a resolution of the same degree as that in which the average level is obtained as data of several bits. |
