发明名称 DATA PROCESSOR
摘要 In order to delay the designated data from RZ decoder (36) the entry control latch register (33) is provided on the input side of the RZ decoder (36). The command signal through a memory bus (16) is read in program memory control device (12'). The command signal is inputed to command register (92) and through the command decoder (94) , ROM address decoder (96). ROM (read only memory) reads the microcommand signals and temporarily stores them in microcommand register (32). The microcommand signals are composed of 3 register fields (RX, RY, RZ) and function field (FUNC).
申请公布号 KR880001418(B1) 申请公布日期 1988.08.01
申请号 KR19830000823 申请日期 1983.02.28
申请人 HITACHI LTD. 发明人 KATSURA KOHYOH;MAEJIMA HIDEO
分类号 G06F9/38;G06F9/22;G06F9/28 主分类号 G06F9/38
代理机构 代理人
主权项
地址