| 摘要 |
PURPOSE:To improve the performance of a vector processor by comparing the number of clocks needed for the end of the arithmetic result of a vector register with the number of clocks needed for read-out of the contents of said vector register via the subsequent instructions. CONSTITUTION:A vector length register 1 shows the number of vector elements which are executed by the vector arithmetic. The contents of an instruction word register 2 are decoded by a decoder 3. A multiplier 5 multiplies the contents of the register 1 by the value on a signal line 4. The executing time consumed by a working computing element per element is outputted onto a signal line 6 from the decoder 3 and added with the output of the multiplier 5 by an adder 7 to be set at a counter 8 when the execution of an instruction is instructed. The counter 8 continues a count-down operation until the count value is equal to 0 and stopped thereafter. While a write mode flag 9 is set when the execution is instructed and then reset when a decoder 10 detects that the count value of the counter 8 is equal to the prescribed value. A comparator 11 compares the contents of the multiplier 5 with those of the counter 8. In such a way, the performance of a vector processor is improved. |
