| 摘要 |
PURPOSE:To improve the performance of a vector processor by controlling the writing inhibition period of a vector register in accordance with the reading speed of the vector register. CONSTITUTION:An output signal line 4 outputs the clock intervals for transmission of the arithmetic data to a multiplier 5. The multiplier 5 multiplies the contents of a vector length register 1 by the data value on the line 4 and sets the result of this multiplication at a counter 6. Hereafter the counter 6 continues the count-down actions until the count value is equal to '0'. A read mode flag 8 is set to show that a vector register is reading data and at the same time a writing inhibition flag 7 is also set. A comparator 9 compares the contents of the register 1 with the count value of the counter 6. Then the flag 7 is set when the coincidence is obtained from said comparison. When a decoder 10 detects that the counter 6 is set at '0' from '1', the flag 8 is reset. In such a way, the performance of a vector processor is improved. |
