| 摘要 |
PURPOSE:To improve the throughput without requiring a complicated interrupt control processing in each central processing unit by individually controlling interrupt requests with an interrupt controller shared among plural central processing units. CONSTITUTION:Central processing units P1-Pn set corresponding to the bit fields of a mask register 4 of an interrupt controller 2 to logic value '1' in an initial state. When an interrupting signal IS is inputted, the bit fields of an interruption requesting register 5 corresponding to said bit fields set to logic value '1' are set to logic value '1', and the interruption requesting signal is sent to interrupt request lines l1-ln. When one central processing unit, for example, P1 is down, this state is sent to the other central processing units P2-Pn, and another central processing unit, for example, P2 writes logic value '0' in the bit field in the mask register 4 corresponding to the central processing unit P1 to mask the central processing unit P1, and simultaneously, the bit field of the interrupt request register is cleared. |
