| 摘要 |
<p>PURPOSE:To efficiently execute data input/output by providing first and second oscillating circuits by which a central arithmetic processing circuit is operated in accordance with respective data input/output speeds of an internal storage circuit and an input/output circuit. CONSTITUTION:In the case of input/output of data D between a central arithmetic processing circuit 11 and an internal storage circuit 14, a driving signal (a) from an oscillating circuit 12a which generates the driving signal (a) of relatively high speed is supplied to the central arithmetic processing circuit 11 by the control of a switching circuit 13, and the circuit 11 is operated at relatively high speed. In the case of input/output of data D between the central arithmetic processing circuit 11 and an input/output circuit 15, a driving signal (b) from an oscillating circuit 12b which generates the driving signal of relatively low speed is supplied to the central arithmetic processing circuit 11, and the circuit 11 is operated at the relatively low speed.</p> |
