发明名称 VITERBI DECODER
摘要 PURPOSE:To reduce excessive enhancement for a high frequency band or a low frequency band due to an equalizing filter, by preparing a coefficient string equivalent to inter-code interference, and providing devices which take the coefficient string and a product of combination strings of a remaining path and a decoding assumptive value, respectively, and an adder/subtractor which reduces each output of a sum of product from an input value. CONSTITUTION:Data strings cm(m=0-n) which represent the intercode interference are held in a register 55. The cm is added on the input on one side of sum of product apparatuses 51-54, and decoding systems (j) and bim are added on the input on the other side, and to each of the outputs of the sum of product apparatuses, an assumptive amplitude value aij in the combination system of the remaining path (i) (0 or 1) and an assumptive decoding value (j) (0 or 1) are outputted. A sample input yk is added on the input on one side of the adders 30-33, and the aij is added on the input on the other side. The output of the adder 44 is held at a latch 45, and is used in the input of the next data, A probable path is selected by the outputs of comparators 40 and 41. Registers 46 and 47 are shifted to the right at every input of the data, and 0 and 1 are inputted to a left end, and a decoding value overflowing from a right end is selected and outputted by a switch 56.
申请公布号 JPS63185228(A) 申请公布日期 1988.07.30
申请号 JP19870017692 申请日期 1987.01.28
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MATSUSHITA KOJI;IKETANI AKIRA
分类号 H04L25/08;G11B20/10;H03M13/23 主分类号 H04L25/08
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