| 摘要 |
PURPOSE:To obtain an n-fold operation speed of cache memory blocks by inputting input information to n-number of cache memory blocks in time division and multiplexing and outputting output signals from respective cache memory blocks. CONSTITUTION:A demultiplexer 1 sends input address signals A1 and A2 to latch circuits 11 and 12 in time division in accordance with a clock CLK 1. Outputs 121 and 122 of latch circuits 11 and 21 are discriminated in directories 21 and 22 with respect to hit or mishit. Output signals 131 and 141 from directories access data memories 31 and 32 to obtain outputs 151 and 152. Outputs 151 and 152 are multiplexed by a multiplexer 2 after inputted to latch circuits 41 and 42. Hit signals 132 and 142 from directories 21 and 22 are multiplexed by a multiplexer 3 to become a hit signal HOUT.
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