发明名称 COMPARISON CIRCUIT
摘要 PURPOSE:To decrease the number of elements, and to execute a processing at a high speed by constituting a comparison circuit of a NOR circuit and an inverter circuit. CONSTITUTION:A 1 bit comparison circuit consists of inverter circuits 23, 24 connected to input terminals 101-1, 101-2, respectively, to which a bit to be compared is inputted, and NOR circuits 21, 22 in which inputs of the respective input terminals 101-1, 102-1 become one input, respectively, and outputs from the circuits 23, 24 become the other input, respectively. The output of the circuit 21 becomes '1', when the input 101-1 is larger than the input of the input 102-1, and the output of the circuit 22 becomes '1', at the time of the contrary. By a deciding circuit 2-1 for inputting two pieces 1-1, 1-2 of said 1 bit comparison circuits and deciding whether they are large or small, a multi-bit comparison circuit is constituted. In such a way, since the NOR circuit and the inverter circuit are connected symmetrically, when an integrated circuit is formed, the area can be reduced, and the processing can be executed at a high speed.
申请公布号 JPS63184828(A) 申请公布日期 1988.07.30
申请号 JP19870016880 申请日期 1987.01.27
申请人 NEC CORP 发明人 YAMASHINA MASAKATSU
分类号 G06F7/02 主分类号 G06F7/02
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