发明名称 INDENTIFICATION CLOCK GENERATING CIRCUIT
摘要 PURPOSE:To always correctly set the phase between a clock and a data by using a variable point between specified 1st and 2nd points controlling the clock-generating circuit based on the informations between a second variable point and a first variable point, and between the first variable point and a subsequent second variable point to generate an identification clock. CONSTITUTION:The clock-generating circuit 400 consists of a variable frequency oscillator 11. In the circuit 400, the 1st variable point of a reproduced digital signal which is not latched by an identifying clock, and the 2nd variable point which is a rising or falling point a clock C are used, and the circuit is controlled based on the information between the second variable point and the first variable point and between the first variable point and the subsequent second variable point to generate the identification clock. Hence the raising or descending the regenerated data is always set at the center of a period of the clock even if the jitter in a running system or the variable speed irrespective of the modulation regulation.
申请公布号 JPS63184966(A) 申请公布日期 1988.07.30
申请号 JP19870016052 申请日期 1987.01.28
申请人 HITACHI LTD 发明人 UMEMOTO MASUO;ETO YOSHIZUMI;SAWAMURA HIDEHIKO;IZUMIDA MORIJI;KATAYAMA HITOSHI
分类号 G11B20/14;H03K5/00 主分类号 G11B20/14
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