| 摘要 |
PURPOSE:To increase C4/C3, wherein C3 denotes a capacitance between a gate electrode and a floating gate electrode and C4 denotes a capacitance between the floating gate electrode and the dry diffused layer of a semiconductor substrate and facilitate the operation of a memory transistor with a low voltage by forming a tunnel current region between the gate electrode and the floating gate electrode. CONSTITUTION:A floating gate electrode 110a is formed on 1st insulating film (gate insulating film) 109 so as to be extended over a channel region 130 and a drain diffused layer 116c. The whole surface of the floating gate electrode 110a is covered with 2nd insulating film 111 with a relatively large thickness of, for instance, not less than 1000 Angstrom and a tunnel current region 12 is provided in a part of the thick 2nd insulating film 111. A gate electrode 113 is formed so as to cover the tunnel current region 112. Therefore, a capacitance C3 between the floating gate 110a and the gate electrode 113 can be substantially reduced owing to the large film thickness of the 2nd insulating film 111 and the small area of the gate electrode 113. Even if a capacitance C4 between the floating gate electrode 110a and the drain diffused layer 116c remains unchanged, C4/C3 can be increased. |
