发明名称 SHARED RAM ACCESSING SYSTEM
摘要 PURPOSE:To respond to the change of a storage position, by writing a data which specifies an area prohibited to write the data from a second processor on another RAM by a first processor after applying a power source, and deciding whether an address is a prohibited area or not at the time of accessing to the second processor. CONSTITUTION:When a shared RAM 14 is accessed by a first and a second processor units 11 and 12, an address decoder 15 is provided on the unit 11 side, and an address decoder RAM 16 on the unit 12 side, respectively. And in the unit 12, the data representing possible/impossible to be written is supplied on each address of the RAM 14, and after the power source being applied, the unit 11 writes the data on the RAM 16. Furthermore, when the unit 12 accesses to the RAM 14 in such state, the data possible/impossible to be written is read from the corresponding address of the RAM 16, and if the area is the prohibited area, no write of the data on the RAM 14 is performed.
申请公布号 JPS63184154(A) 申请公布日期 1988.07.29
申请号 JP19870016445 申请日期 1987.01.27
申请人 FANUC LTD 发明人 YAMAUCHI TAKASHI
分类号 G06F15/16;G06F12/00;G06F12/14;G06F15/167;G06F15/177;G06F21/02 主分类号 G06F15/16
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