| 摘要 |
PURPOSE:To execute a readout operation at a high speed by transferring the potential of a complementary data line to a complementary common data line through an amplifying MOSFET provided in accordance with the respective complementary data lines. CONSTITUTION:At the time point when a selecting operation for word lines W0-Wm has been ended, timing signals phipa1, phipa2 are activated and a sense amplifier SA is activated, and readout signals outputted to complementary data lines D0, the inverse of D0 from a memory array M-ARY are amplified by the amplifier SA and become quickly binary readout signals. There readout signals are transferred to complementary common data lines CD, the inverse of CD through amplifying MOSFETs Q7, Q15, Q8, Q16-Q9, Q17, Q10 and Q18 of a column switch CSW, and amplified by a main amplifier MA. Therefore, the amplifying action of the readout signal by the amplifier SA is not affected by the floating capacity of the data lines CD, the inverse of CD. Accordingly, a readout operation as a dynamic type RAM is executed at a high speed.
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