| 摘要 |
PURPOSE:To automatically execute refreshing while keeping pace with a serial operation by detecting a fact that there is no random access to a memory string, at the time of an output/input operating state of serial information, and refreshing the memory string by using a clock signal. CONSTITUTION:At the time of a serial output operation, a synchronizing control circuit TC generates a refresh control signal phirf of 1/4 frequency division of a signal SC (phi), while a column address strobe RAS holds 'H' for a prescribed time T (for instance, a four-period portion of a clock signal SC), in other words, when it is detected that there is no random access to a RAM, and a circuit REFC executes address stepping and switches an input part of a column address buffer R-ADB at every arrival of phirf, and refreshes the RAM. In the course of a parallel execution of a serial operation and refresh, if the signal RSA changes to 'L' and random access is executed to the RAM, the circuit TC suspends refresh, and the random access is executed preferentially. According to this constitution, refresh can be executed automatically.
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