| 摘要 |
PURPOSE:To reduce the influence of the bit length of a multiplicand and to realize the high-speed multiplication by using a carry preserving adder which adds >=3 inputs together and a carry transmitting adder which adds the carry output of the carry preserving adder and the sum output which perform no carry. CONSTITUTION:A bit inverter 10 is provided at the input side of a carry preserving adder 16 and the 2-tier series connection of a 2-input/1-output carry transmitting arithmetic circuit is replaced with the combination of the 3-input/2-output adder 16 and a 2-input/1-output carry transmitting adder 17. The adder 16 produces 2 bits having their bit positions corresponding to 2 outputs from only 3 bits having their bit positions corresponding to 3 inputs respectively without producing the carry transmission. As a result, an addition job is carried out at an extremely high speed and the multiplication processing is possible at a high speed with the processing time having no relation with the addition bit length in comparison with a carry transmitting adder with which the equal bit length is secured as the bit length is increased. |
