| 摘要 |
PURPOSE:To realize the test of all cells of a temporary memory circuit regardless of the time slot replacing action of a primary signal, by changing a monitor time slot over all addresses in the temporary memory circuit. CONSTITUTION:A monitor time slot is produced at an optional position of the input data 101 by a delay circuit 20 and a selection circuit 21. A test signal 106 is put into said time slot by a selection circuit 23 and written into a corresponding writing address 102. Then the signal 106 is read out via a random address. The write signals are increased one by one with insertion of the monitor time slot. Thus a comparator 25 compares the test signal address data 107, i.e., the output of a test signal address counter 24 with the read address data 103. Then the input 101 is corrected by a selection circuit 26 and read out. Then the signal 106 is read out. The data input 101 is collated with the signal 106 by a test signal collation circuit 16 or 17. In the next cycle the monitor time slots are decreased one by one for check of the next address.
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