| 摘要 |
PURPOSE:To minimize the effect of a bit error by applying serialparallel conversion to a serial time division multiple line and using plural FiFos connected in parallel so as to apply speed conversion to the result. CONSTITUTION:A data stored in a FiFo12 is latched in a D flip-flop 13 and outputted from a B flip-flop 13 of each channel (n) by a clock generated by a frame synchronizing signal (B/8XnHz) at the output side inputted to a terminal DC sequentially. Moreover, a time slot synchronizing clock of B/8Hz is inputted to a terminal SiL of a shift register 14, where parallel-serial conversion is applied and shifted/loaded sequentially and outputted as a time division multiplex output data 2 of B/8bs different transmission speed from that of the input. Then the n-set of FiFos 12 and the D flip-flops 13 constitute a converting section. Even if missing bit or bit shift due to duplicated bits takes place caused by a fault of a transmission line, so long as the frame synchronizing signal is normal, the effect of the fault does not given onto the succeeding data.
|
