| 摘要 |
PURPOSE:To reduce the power consumption of the circuit and to decrease the fluctuation of a detection time delay of a trigger signal by synchronizing an input signal by either leading or trailing of a clock signal which coming faster in synchronizing the input signal by the clock signal and counting the clock signal in this case while the phase is inverted by 180 deg.. CONSTITUTION:A clock identification inverting circuit 17 outputs a clock signal 2 while inverting the phase when a Q output of a D flip-flop 12 goes to a high potential earlier than the Q output of the D flip-flop 10. In other cases, the circuit 17 outputs the clock signal 2 as it is. Thus, the output 7 becomes a clock signal synchronized with a signal rising first after the leading of a trigger signal in two signals, clock signal 2 and inverted clock signal 3. Thus, the phase shift of the clock signal synchronizing the trigger signal is suppressed to a half of the clock signal at maximum with respect to the trigger signal input. Thus, the fluctuation of the time delay of the pulse signal with respect to the inputted trigger signal is halved.
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