| 摘要 |
<p>The CMOS circuit comprising regions n (20a) and regions p (32a) formed in a silicon substrate (2), a first mask is provided on the substrate of which the patterns (10a) mask the regions p (32a); a second mask (22a) is formed on the substrate in order to mask the regions n (20a), the first mask of which the flanks present in their upper part an inclined profile being selectively etchable with respect to the second mask; the patterns of the first and second masks being disjointed and fixing therebetween the position and the width of the insulating trenches (24); the trenches are formed by etching the susbtrate and the first mask and the substrate are etched simultaneously in order to form in the upper part (24a) of each trench and in contact with the regions p flanks inclined (26) with respect to the upper surface of the substrate so that the cross-section of the trenches (24) widens towards the upper surface of the substrate.</p> |
