发明名称 LOGIC CIRCUIT EQUIPPED WITH TEST FACILITATING FUNCTION
摘要 PURPOSE:To test function blocks one by one and to facilitate the test by holding signals of a function block signal input line and a signal output line by signal holding/transferring means at the time of the test, and leading the signal out, and comparing them with an expected value. CONSTITUTION:A control signal CONT is set to 1 at the time of the testing operation, FF circuits in registers 31 (311-3110) for scanning are connected in series to enter a shift register state, and they are disconnected from respective signal lines 21-30. Then when a clock signal CLK is inputted only once, a signal selected by each selector circuit previously is latched by an FF circuit at the rising timing of the CLK and outputted at the falling timing of the CLK. Then the CLK is supplied as many times as necessary and the latch signals of the FF circuits are transferred to trailing registers 31 and led out from a register 318. This output is compared with the expected value to perform the test.
申请公布号 JPS63182585(A) 申请公布日期 1988.07.27
申请号 JP19870015816 申请日期 1987.01.26
申请人 TOSHIBA CORP 发明人 MORI SHOJIRO
分类号 H03K19/00;G01R31/28;G01R31/3185 主分类号 H03K19/00
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