| 摘要 |
PURPOSE:To improve a fault detection rate by providing an FF circuit which includes latches receiving 1st and 2nd input data with 1st and 2nd clock signals and latches receiving output signals of the latches with 3rd and 4th clock signals or inverted signals. CONSTITUTION:The latch master FM of FFs 1-(n) consists basically of NAND gate circuit NAGs 2 and 3, which are connected crossing each other to form a latch configuration. When data and a clock signal (CLK) inputted to terminals D1 and C1 through inverter circuits N1 and N3 are both at H, the output of an OR gate circuit OG1 is at L. The output of an OG2 is at L when the input data and CLK are at H. An OG3 is at L when the input data is at L and the CLK is at H, and the output of an OG4 is at L when the input data and CLK are at H. When the CLKs (C1 and C2) are at L, the OG1-OG4 are all at H and the NAND gates NAG2 and NAG3 are at H or L to enter a latch state, so that they are inputted to a slave latch FS. |
