| 摘要 |
PURPOSE:To rapidly and effectively switch a bus by transmitting simultaneous bus switching signals from a bus switching controller to switch the bus in a processor and transmitting an individual bus switching signal to a processor which cannot recognize the receiving of a bus switching completion signal. CONSTITUTION:A bus switching control part 17, after the simultaneous bus switching signals are transmitted, transmits a reading request to a bus switching completion signal receiving storing part 18 and reads the address of the processor which does not receive the bus switching completion signal 42. The bus switching control part 17, when there is the processor receiving no bus switching completion signal 42, transmits the address of the processor and a control signal to an individual bus switching signal transmitting part 16. Then, the individual bus switching signal transmitting part 16 transmits the individual bus switching signal 41 to the processor via a signal transmitting part 13 and a bus switching part 12. Thereby, the processor receiving no bus switching completion signal 42 is recognized to transmit the individual bus switching signal 41 and effectively switch the bus.
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