| 摘要 |
PURPOSE:To rapidly switch a bus and to prevent the centralization of a bus switching completion signal by providing a means for previously storing delay information in a processor and a means for delaying the transmission of the bus switching completion signal based on the delay information stored when the bus switching is completed. CONSTITUTION:A bus switching signal is transferred to a bus switching control part 32 according to a signal split function and when the bus switching control part 32 receives the switching signal, it transmits a control signal to a bus switching part 31 to switch the bus. Then, the contents of a register 36 are read and when a time determined by the value elapses, the bus switching completion signal is transmitted to the bus 20 through a signal transmitting part 34 and the bus switching part 31. At this time, since the control signal for switching the bus has already transmitted to the bus switching part 31, the bus switching completion signal is switched and transmitted to a bus switching controller 10 through the currently used bus. Thereby, a receiving buffer 11 is prevented from being completely full to receive a receiving completion signal.
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