发明名称 SAMPLE AND HOLDING CIRCUIT
摘要 PURPOSE:To sample stably a high speed signal by setting the 1/2 period of a resonance circuit comprising a hold capacitor and an inductance to a similar degree to the turning on time of a diod bridge. CONSTITUTION:The inductance Lr is connected in series to the diode bridge and the hold capacitor Cs. The 1/2 period of the resonance circuit comprising the hold capacitor Cs and the inductance Lr is set approximately to a time during only the diode bridge is turned on. In such constitution, the voltage Vcs charged to the hold capacitor Cs after the diode bridge is completely turned off takes a larger value than the peak voltage Vd at the output point of the diode bridge, thus the sample holding circuit capable to sample stably the high speed signal is realized by the relatively simple constitution.
申请公布号 JPS63181200(A) 申请公布日期 1988.07.26
申请号 JP19870012692 申请日期 1987.01.22
申请人 YOKOGAWA ELECTRIC CORP 发明人 YAMANAKA KATSUHIKO;KITAZONO MICHIAKI;OGAWA TETSURO
分类号 G11C27/02 主分类号 G11C27/02
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