| 摘要 |
<p>PURPOSE:To always have a steady phase difference between the 2nd reading clock signal and a writing clock signal by delivering the inverted signal of the 1st reading clock signal in the form of the 2nd reading clock signal. CONSTITUTION:A writing clock signal is applied to a terminal 18 from the 1st clock source. A counter circuit 15 receives a writing clock signal at one of its two input terminals and counts the phase difference between two input signals. A comparator 16 compares the count output given from the circuit 15 with a prescribed constant 21 and delivers a coincidence signal when the coincidence is obtained. The 1st reading clock signal is applied to a terminal 19 from the 2nd clock source and then supplied to an inverting circuit 17. The circuit 17 performs the in-phase and reverse phase output operations alternately to the 1st reading clock signal every time the coincidence signal is delivered from the comparator 16. These outputs are supplied to the circuit 15 in the form of the 2nd reading clock signals.</p> |
